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Low Power, High Speed Rail-to-Rail Input/Output Amplifier AD8029/AD8030/AD8040
FEATURES
Low power 1.3 mA supply current/amplifier High speed 125 MHz, -3 dB bandwidth (G = +1) 60 V/s slew rate 80 ns settling time to 0.1% Rail-to-rail input and output No phase reversal, inputs 200 mV beyond rails Wide supply range: 2.7 V to 12 V Offset voltage: 6 mV max Low input bias current +0.7 A to -1.5 A Small packaging SOIC-8, SC70-6, SOT23-8, SOIC-14, TSSOP-14
NC 1 -IN 2 +IN 3 -VS 4
CONNECTION DIAGRAMS
8 7 6 5
DISABLE +VS VOUT NC
03679-A-004
VOUT 1 -VS 2 +IN 3
6
+VS
+
-
5
DISABLE
03679-A-002
NC = NO CONNECT
4
-IN
Figure 1. SOIC-8 (R)
Figure 2. SC70-6 (KS)
VOUT 1 1 -IN 1 2 +IN 1 3
VOUT 1 1 -IN 1 2 +IN 1 3 -VS 4
8 7 6 5
14 V OUT 4 13 -IN 4 12 +IN 4 11 -VS 10 +IN 3
03679-A-001
+VS +VOUT 2
03679-A-003
+VS 4 +IN 2 5 -IN 2 6 VOUT 2 7
APPLICATIONS
Battery-powered instrumentation Filters A-to-D drivers Buffering
-IN 2 +IN 2
9 8
-IN 3 VOUT 3
Figure 3. SOIC-8(R) and SOT23-8 (RJ)
Figure 4. SOIC-14 (R) and TSSOP-14 (RU)
GENERAL DESCRIPTION
The AD8029 (single), AD8030 (dual), and AD8040 (quad) are rail-to-rail input and output high speed amplifiers with a quiescent current of only 1.3 mA per amplifier. Despite their low power consumption, the amplifiers provide excellent performance with 125 MHz small signal bandwidth and 60 V/s slew rate. ADI's proprietary XFCB process enables high speed and high performance on low power. This family of amplifiers exhibits true single-supply operation with rail-to-rail input and output performance for supply voltages ranging from 2.7 V to 12 V. The input voltage range extends 200 mV beyond each rail without phase reversal. The dynamic range of the output extends to within 40 mV of each rail.
VOLTAGE (V)
powered systems with large bandwidth requirements to high speed systems where component density requires lower power dissipation. The AD8029/AD8030 are the only low power, rail-to-rail input and output high speed amplifiers available in SOT23 and SC70 micro packages. The amplifiers are rated over the extended industrial temperature range, -40C to +125C.
5.0 INPUT 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 G = +1 0.5 VS = +5V RL = 1k TIED TO MIDSUPPLY 0 TIME (s) OUTPUT
The AD8029/AD8030/AD8040 provide excellent signal quality with minimal power dissipation. At G = +1, SFDR is -72 dBc at 1 MHz and settling time to 0.1% is only 80 ns. Low distortion and fast settling performance make these amplifiers suitable drivers for single-supply A/D converters. The versatility of the AD8029/AD8030/AD8040 allows the user to operate the amplifiers on a wide range of supplies while consuming less than 6.5 mW of power. These features extend the operation time in applications ranging from batteryRev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
1s/DIV
03679-A-010
Figure 5. Rail-to-Rail Response
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD8029/AD8030/AD8040 TABLE OF CONTENTS
Specifications..................................................................................... 3 Specifications with 5 V Supply ................................................. 3 Specifications with +5 V Supply ................................................. 4 Specifications with +3 V Supply ................................................. 5 Absolute Maximum Ratings............................................................ 6 Maximum Power Dissipation ..................................................... 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 15 Input Stage................................................................................... 15 Output Stage................................................................................ 15 Applications..................................................................................... 16 Wideband Operation ................................................................. 16 Output Loading sensitivity........................................................ 16 Disable Pin .................................................................................. 17 Circuit Considerations .............................................................. 18 Design Tools and Technical Support ....................................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide............................................................................... 20 ESD Caution................................................................................ 20
REVISION HISTORY
Revision A 11/03--Data Sheet Changed from Rev. 0 to Rev. A Change Page
Added AD8040 part .......................................................Universal Change to Figure 5 ....................................................................... 1 Changes to Specifications ............................................................ 3 Changes to Figures 10-12............................................................ 7 Change to Figure 14 ..................................................................... 8 Changes to Figures 20 and 21 ..................................................... 9 Inserted new Figure 36............................................................... 11 Change to Figure 40 ................................................................... 12 Inserted new Figure 41............................................................... 12 Added Output Loading Sensitivity section ............................. 16 Changes to Table 5...................................................................... 17 Changes to Power Supply Bypassing section .......................... 18 Changes to Ordering Guide ...................................................... 20
Rev. A | Page 2 of 20
AD8029/AD8030/AD8040 SPECIFICATIONS
SPECIFICATIONS WITH 5 V SUPPLY
Table 1. VS = 5 V @ TA = 25C, G = +1, RL = 1 k to ground, unless otherwise noted. All specifications are per amplifier.
Parameter
DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) Input Voltage Noise Input Current Noise Crosstalk (AD8030/AD8040) DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current1
Conditions
G = +1, VO = 0.1 V p-p G = +1, VO = 2 V p-p G = +2, VO = 0.1 V p-p G = +1, VO = 2 V Step G = -1, VO = 2 V Step G = +2, VO = 2 V Step fC = 1 MHz, VO = 2 V p-p fC = 5 MHz, VO = 2 V p-p f = 100 kHz f = 100 kHz f = 5 MHz, VIN = 2 V p-p PNP Active, VCM = 0 V NPN Active, VCM = 4.5 V TMIN to TMAX NPN Active, VCM = 4.5 V TMIN to TMAX PNP Active, VCM = 0 V TMIN to TMAX Vo = 4.0 V
Min
80 14
Typ
125 19 6 62 63 80 -74 -56 16.5 1.1
Max
Unit
MHz MHz MHz V/s V/s ns dBc dBc nV/Hz pA/Hz dB
-79
1.6 2 30 0.7 1 -1.7 2 0.1 74 6 2 -5.2 to +5.2 90 -VS + 0.8 -6.5 -VS + 1.2 0.2 5 6 1.3 -2.8 0.9
mV mV V/C A A A A A dB M pF V dB V A V A ns ns
Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio DISABLE PIN (AD8029) DISABLE Low Voltage DISABLE Low Current DISABLE High Voltage DISABLE High Current Turn-Off Time Turn-On Time OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing Short-Circuit Current Off Isolation (AD8029) Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Quiescent Current (Disabled) Power Supply Rejection Ratio
1
65
VCM = -4.5 V to +3 V, RL = 10 k
80
50% of DISABLE to <10% of Final VO, VIN = -1 V, G = -1 50% of DISABLE to <10% of Final VO, VIN = -1 V, G = -1
150 85
VIN = +6 V to -6 V, G = -1 RL = 1 k RL = 10 k Sinking and Sourcing VIN = 0.1 V p-p, f = 1 MHz, DISABLE = Low 30% Overshoot
55/45 -VS + 0.22 -VS + 0.05 170/160 -55 20 2.7 1.4 12 1.5 200 +VS - 0.22 +VS - 0.05
ns V V mA dB pF V mA A dB
DISABLE = Low Vs 1 V 73
150 80
Plus, +, (or no sign) indicates current into pin; minus (-) indicates current out of pin.
Rev. A | Page 3 of 20
AD8029/AD8030/AD8040
SPECIFICATIONS WITH +5 V SUPPLY
Table 2. VS = 5 V @ TA = 25C, G = +1, RL = 1 k to midsupply, unless otherwise noted. All specifications are per amplifier.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) Input Voltage Noise Input Current Noise Crosstalk (AD8030/AD8040) DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current1 Conditions G = +1, VO = 0.1 V p-p G = +1, VO = 2 V p-p G = +2, VO = 0.1 V p-p G = +1, VO = 2 V Step G = -1, VO = 2 V Step G = +2, VO = 2 V Step fC = 1 MHz, VO = 2 V p-p fC = 5 MHz, VO = 2 V p-p f = 100 kHz f = 100 kHz f = 5 MHz, VIN = 2 V p-p PNP Active, VCM = 2.5 V NPN Active, VCM = 4.5 V TMIN to TMAX NPN Active, VCM = 4.5 V TMIN to TMAX PNP Active, VCM = 2.5 V TMIN to TMAX Vo = 1 V to 4 V 65 Min 80 13 Typ 120 18 6 55 60 82 -73 -55 16.5 1.1 -79 1.4 1.8 25 0.8 1 -1.8 2 0.1 74 6 2 -0.2 to +5.2 90 -VS + 0.8 -6.5 -VS + 1.2 0.2 155 90 5 6 1.2 -2.8 0.9 Max Unit MHz MHz MHz V/s V/s ns dBc dBc nV/Hz pA/Hz dB mV mV V/C A A A A A dB M pF V dB V A V A ns ns
Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio DISABLE PIN (AD8029) DISABLE Low Voltage DISABLE Low Current DISABLE High Voltage DISABLE High Current Turn-Off Time Turn-On Time OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing Short-Circuit Current Off Isolation (AD8029) Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Quiescent Current (Disabled) Power Supply Rejection Ratio
1
VCM = 0.25 V to 2 V, RL = 10 k
80
50% of DISABLE to <10% of Final VO, VIN = -1 V, G = -1 50% of DISABLE to <10% of Final VO, VIN = -1 V, G = -1
VIN = -1 V to +6 V, G = -1 RL = 1 k RL = 10 k Sinking and Sourcing Vin = 0.1 V p-p, f = 1 MHz, DISABLE = Low 30% Overshoot
45/50 -VS + 0.17 -VS + 0.04 95/60 -55 15 2.7 12 1.5 200 +VS - 0.17 +VS - 0.04
ns V V mA dB pF V mA A dB
DISABLE = Low VS 1 V
73
1.3 140 80
Plus, +, (or no sign) indicates current into pin; minus (-) indicates current out of pin.
Rev. A | Page 4 of 20
AD8029/AD8030/AD8040
SPECIFICATIONS WITH +3 V SUPPLY
Table 3. VS = +3 V @ TA = 25C, G = +1, RL = 1 k to midsupply, unless otherwise noted. All specifications are per amplifier.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) Input Voltage Noise Input Current Noise Crosstalk (AD8030/AD8040) DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current1 Input Bias Current1 Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio DISABLE PIN (AD8029) DISABLE Low Voltage DISABLE Low Current DISABLE High Voltage DISABLE High Current Turn-Off Time Turn-On Time OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing Short-Circuit Current Off Isolation (AD8029) Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Quiescent Current (Disabled) Power Supply Rejection Ratio
1
Conditions G = +1, VO = 0.1 V p-p G = +1, VO = 2 V p-p G = +2, VO = 0.1 V p-p G = +1, VO = 2 V Step G = -1, VO = 2 V Step G = +2, VO = 2 V Step fC = 1 MHz, VO = 2 V p-p fC = 5 MHz, VO = 2 V p-p f = 100 kHz f = 100 kHz f = 5 MHz, VIN = 2 V p-p PNP Active, VCM = 1.5 V NPN Active, VCM = 2.5 V TMIN to TMAX NPN Active, VCM = 2.5 V TMIN to TMAX PNP Active, VCM = 1.5 V TMIN to TMAX Vo = 0.5 V to 2.5 V
Min 80 13
Typ 112 18 6 55 57 110 -72 -60 16.5 1.1 -80 1.1 1.6 24 0.7 1 -1.5 1.6 0.1 73 6 2 -0.2 to +3.2 88 -VS + 0.8 -6.5 -VS + 1.2 0.2 165 95
Max
Unit MHz MHz MHz V/s V/s ns dBc dBc nV/Hz pA/Hz dB
5 6 1.2 -2.5 0.9
64
mV mV V/C A A A A A dB M pF V dB V A V A ns ns
VCM = 0.25 V to 1.25 V, RL = 10 k
78
50% of DISABLE to <10% of Final VO, VIN = -1 V, G = -1 50% of DISABLE to <10% of Final VO, VIN = -1 V, G = -1
VIN = -1 V to +4 V, G = -1 RL = 1 k RL = 10 k Sinking and Sourcing VIN = 0.1 V p-p, f = 1 MHz, DISABLE = Low 30% Overshoot
75/100 -VS + 0.09 -VS + 0.04 80/40 -55 10 2.7 12 1.4 200 +VS - 0.09 +VS - 0.04
ns V V mA dB pF V mA A dB
DISABLE = Low VS 1 V
70
1.3 145 76
Plus, +, (or no sign) indicates current into pin; minus (-) indicates current out of pin.
Rev. A | Page 5 of 20
AD8029/AD8030/AD8040 ABSOLUTE MAXIMUM RATINGS
Table 4. AD8029/AD8030/AD8040 Stress Ratings
Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 12.6 V See Figure 6 VS 0.5 V 1.8 V -65C to +125C -40C to +125C 300C 150C
PD = Quiescent Power + (Total Drive Power - Load Power)
V V PD = (VS x I S ) + S x OUT 2 RL VOUT 2 - RL
RMS output voltages should be considered. If RL is referenced to VS-, as in single-supply operation, then the total drive power is VS x IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply:
PD = (VS x I S ) +
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(VS /4 )2
RL
In single-supply operation with RL referenced to VS-, worst case is VOUT = VS/2. Airflow will increase heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the JA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps, as discussed in the PCB Layout section. Figure 6 shows the maximum safe power dissipation in the package versus the ambient temperature for the SOIC-8 (125C/W), SOT23-8 (160C/W), SOIC-14 (90C/W), TSSOP-14 (120C/W), and SC70-6 (208C/W) packages on a JEDEC standard 4-layer board. JA values are approximations.
2.5
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8029/AD8030/ AD8040 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8029/AD8030/AD8040. Exceeding a junction temperature of 175C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (JA), ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as TJ = TA + (PD x JA) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 x IOUT, some of which is dissipated in the package and some in the load (VOUT x IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package.
MAXIMUM POWER DISSIPATION (W)
2.0 SOIC-14 1.5 SOIC-8 1.0 SOT-23-8
TSSOP-14
0.5
SC70-6
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (C)
Figure 6. Maximum Power Dissipation
Output Short Circuit
Shorting the output to ground or drawing excessive current from the AD8029/AD8030/AD8040 could cause catastrophic failure.
Rev. A | Page 6 of 20
03679-A-018
AD8029/AD8030/AD8040 TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: VS = 5 V (TA = 25C, RL = 1 k tied to midsupply, unless otherwise noted.)
1 0
NORMALIZED CLOSED-LOOP GAIN (dB)
0.2
NORMALIZED CLOSED-LOOP GAIN (dB)
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 0.1 VO = 0.1V p-p 1 10 FREQUENCY (MHz) G = +2 RF = RG = 1k G = +10 RF = 9k, RG = 1k
G = -1 RF = RG = 1k
DASHED LINES: VOUT = 2V p-p 0.1 SOLID LINES: VOUT = 0.1V p-p 0 -0.1 G = +1 -0.2 -0.3 -0.4 G = +2 -0.5 -0.6 -0.7 -0.8 1 10 FREQUENCY (MHz)
RF = 1k
G = +1 RF = 0
100
1000
03679-0-004
100
03679-A-011
Figure 7. Small Signal Frequency Response for Various Gains
Figure 10. 0.1 dB Flatness Frequency Response
1 0 -1
G = +1 VO = 0.1V p-p 5V
1 +3V
NORMALIZED CLOSED-LOOP GAIN (dB)
0 -1 -2 -3 -4 -5 -6 -7 +3V -8
G = +2 VO = 0.1V p-p RF = 1k
CLOSED-LOOP GAIN (dB)
-2 -3 -4 -5 -6 -7 -8 1 10 100 FREQUENCY (MHz) 1000
03679-0-005
5V
+5V
+5V
1
10 FREQUENCY (MHz)
100
03679-A-012
Figure 8. Small Signal Frequency Response for Various Supplies
Figure 11. Small Signal Frequency Response for Various Supplies
1 0 -1
G = +1 VO = 2V p-p 5V
1
NORMALIZED CLOSED-LOOP GAIN (dB)
0 -1
G = +2 VO = 2V p-p
RF = 1k
CLOSED-LOOP GAIN (dB)
VS = 5 -2 VS = +5 -3 -4 VS = +3 -5 -6 -7 -8
-2 +3V -3 -4 -5 -6 +5V -7 -8 1 10 FREQUENCY (MHz) 100
03679-0-006
1
10 FREQUENCY (MHz)
100
03679-A-013
Figure 9. Large Signal Frequency Response for Various Supplies
Figure 12. Large Signal Frequency Response for Various Supplies
Rev. A | Page 7 of 20
AD8029/AD8030/AD8040
6 G = +1 5 V = 0.1V p-p O 4 3
2
20pF 10pF
CLOSED-LOOP GAIN (dB)
G = +1 1 VO = 0.1V p-p 0 -1 -2 -3 -4 -5 -6 -7 -8 VICM = VS- + 0.2V
VICM = VS+ - 0.2V VICM = 0V
CLOSED-LOOP GAIN (dB)
2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 1
5pF
0pF
10 100 FREQUENCY (MHz)
1000
03679-0-010
1
10 100 FREQUENCY (MHz)
1000
03679-0-013
Figure 13. Small Signal Frequency Response for Various CLOAD
Figure 16. Small Signal Frequency Response for Various Input Common-Mode Voltages
2 1 0 -40C -1 -2 -3 -4 -5 -6 1 10 FREQUENCY (MHz) 100
03679-0-014
1
NORMALIZED CLOSED-LOOP GAIN (dB)
0 -1 -2 -3 -4 -5 -6 -7 -8 1 10 FREQUENCY (MHz) 2V p-p 1V p-p 0.1V p-p
G = +2 RF = 1k
G = +1 VO = 0.1V p-p
+125C +85C +25C
100
03679-A-014
Figure 14. Frequency Response for Various Output Amplitudes
CLOSED-LOOP GAIN (dB)
225
Figure 17. Small Signal Frequency Response vs. Temperature
80 70
1 0
OPEN-LOOP PHASE (Degrees)
G = +1 VO = 2V p-p +125C
60
OPEN-LOOP GAIN (dB)
180
-1
CLOSED-LOOP GAIN (dB)
50 40 30 20 10 0 -10 -20 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 0 1G 45 90 135
+25C -2 +85C -3 -4 -40C -5 -6 -7 -8 1 10 FREQUENCY (MHz) 100
03679-0-015
03679-0-054
Figure 15. Open-Loop Gain and Phase vs. Frequency
Figure 18. Large Signal Frequency Response vs. Temperature
Rev. A | Page 8 of 20
AD8029/AD8030/AD8040
-35 G = +1 VOUT = 2V p-p RL = 1k -45 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE -55
-40 G = +1 VOUT = 2V p-p -50 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
-60
-65 VS = +3V -75
-70 RL = 1k -80
-85 VS = +5V -95 VS = 5V
-90 RL = 5k -100 RL = 2k
-105 0.01
0.1 1 FREQUENCY (MHz)
10
03679-0-016
-110 0.01
0.1 1 FREQUENCY (MHz)
10
03679-0-075
Figure 19. Harmonic Distortion vs. Frequency and Supply Voltage
Figure 22. Harmonic Distortion vs. Frequency and Load
-40
G = +2 FREQ = 1MHz -45 RF = 1k
HARMONIC DISTORTION (dBc)
-40 G = +1 VOUT = 2V p-p FREQ = 1MHz VS = +3V -60 VS = +5V
VS = +5V -50 -55 -60 -65 -70 -75 -80 0.5 VS = +3V
VS = +10V
-50
HARMONIC DISTORTION (dBc)
SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE
-70
-80
-90 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE
1.5
2.5
3.5 4.5 5.5 6.5 7.5 OUTPUT AMPLITUDE (V p-p)
8.5
9.5
-100 1.0
1.5
03679-A-015
2.0 2.5 3.0 3.5 INPUT COMMON-MODE VOLTAGE (V)
4.0
03679-0-020
Figure 20. Harmonic Distortion vs. Output Amplitude
Figure 23. Harmonic Distortion vs. Input Common Mode Voltage
-30 VS = +5V VOUT = 2.0V p-p -40 R = 1k L RF = 1k
HARMONIC DISTORTION (dBc)
1000
100
G = +2 -60 -70 -80 -90 G = +1 -100 -110 0.01 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE 0.1 1 FREQUENCY (MHz) 10
03679-A-016
100
10
G = -1
VOLTAGE NOISE 10 CURRENT NOISE 1
1 10
100
1k
10k 100k FREQUENCY (Hz)
1M
0.1 10M
03679-0-069
Figure 21. Harmonic Distortion vs. Frequency and Gain
Figure 24. Voltage and Current Noise vs. Frequency
Rev. A | Page 9 of 20
CURRENT NOISE (pA/ Hz)
VOLTAGE NOISE (nV/ Hz)
-50
AD8029/AD8030/AD8040
100 75 50 25 0 -25 -50 -75
25mV/DIV 20ns/DIV
100
G = +1 VS = 2.5V
75 50 25 0 -25 -50 -75
G = +1 VS = 2.5V
CL = 20pF CL = 10pF CL = 5pF
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (mV)
25mV/DIV
20ns/DIV
-100 TIME (ns)
03679-0-022
-100 TIME (ns)
03679-0-025
Figure 25. Small Signal Transient Response
Figure 28. Small Signal Transient Response with Capacitive Load
2.5
G = +1
5.0
4V p-p
INPUT 4.5 4.0 3.5
2.0 VS = 2.5V 1.5
OUTPUT VOLTAGE (V)
1.0 2V p-p
VOLTAGE (V)
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5
03679-A-023
3.0 2.5 2.0 1.5 1.0 G = +1 0.5 VS = +5V RL = 1k TIED TO MIDSUPPLY 0 TIME (Seconds) OUTPUT
1s/DIV
03679-0-059
0.5V/DIV TIME (ns)
25ns/DIV
Figure 26. Large Signal Transient Response
Figure 29. Rail-to-Rail Response, G = +1
4 INPUT 3 2
OUTPUT VOLTAGE (V)
4
G = -1 (RF = 1k) RL = 1k VS = 2.5V
OUTPUT VOLTAGE (V)
INPUT 3 2 1 0 -1 -2 -3 OUTPUT
G = +1 RL = 1k VS = 2.5V
1 0 -1 -2 -3
OUTPUT
1V/DIV
200ns/DIV
1V/DIV
200ns/DIV
-4 TIME (ns)
03679-0-024
-4 TIME (ns)
03679-0-027
Figure 27. Output Overdrive Recovery
Figure 30. Input Overdrive Recovery
Rev. A | Page 10 of 20
AD8029/AD8030/AD8040
G = +2 VS = 2.5V +1V VIN (250mV/DIV) VOUT (500mV/DIV) G = +2
+0.1%
+0.1%
VOUT - 2VIN (0.1%/DIV) VOUT - 2VIN (0.1%/DIV)
-0.1%
-0.1%
VOUT (500mV/DIV) -1V
500ns/DIV
03679-0-062
20ns/DIV
03679-0-063
Figure 31. Long-Term Settling Time
Figure 34.0.1% Short-Term Settling Time
-20 -30 -40
0 -10 -20 +PSRR -30
CMRR (dB)
PSRR (dB)
-50 -60 -70 -80
-40 -50 -60 -70 -PSRR -80
-90 -100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 1G
03679-0-078
-90 -100 1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
03679-0-033
Figure 32. Common-Mode Rejection Ratio vs. Frequency
Figure 35. PSRR vs. Frequency
-20 G = +1 RL = 1k DISABLE = LOW VIN = 0.1V p-p
-30
VIN
-40
50
DRIVE AMP 1k
-30
-50 -60
-40
CROSSTALK (dB)
OUTPUT (dB)
LISTEN AMP VOUT 1k
-70 -80
CROSSTALK = 20log
-50
()
VOUT VIN
-90 -100 -110 -120
-60
AD8030 (AMP 2 DRIVE AMP 1 LISTEN)
-70
-80 0.1
1
10 FREQUENCY (MHz)
100
1000
03679-0-055
-130 0.01
0.1
1.0 10 FREQUENCY (MHz)
100
1000
Figure 33. AD8029 Off-Isolation vs. Frequency
Figure 36. AD8030/AD8040 Crosstalk vs. Frequency
Rev. A | Page 11 of 20
03679-A-005
AD8040 (AMP 4 DRIVE AMP 1 LISTEN)
AD8029/AD8030/AD8040
2.5 2.0
4 3 RL = 1k TO MIDSUPPLY G = +1 VS = +3V
INPUT OFFSET VOLTAGE (mV)
1.5
VS = +3V
VS = +5V
VS = +10V
VS = +5V
VS = +10V
INPUT BIAS CURRENT (A)
2 1 0 -1 -2 -3 -4 -1
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -1 0 1 2 3 4 5 6 7 8 9 INPUT COMMON-MODE VOLTAGE (V) 10 11
0
1
03679-0-074
2 3 4 5 6 7 8 9 INPUT COMMON-MODE VOLTAGE (V)
10
11
03679-A-017
Figure 37. Input Bias Current vs. Input Common-Mode Voltage
Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage
-1.0
1.0
4
INPUT BIAS CURRENT (NPN ACTIVE) (A)
INPUT BIAS CURRENT (PNP ACTIVE) (A)
3
NPN ACTIVE
INPUT OFFSET VOLTAGE (mV)
-1.2
0.8
2 VS = 5V 1 0 -1 -2 -3 -4 -40
03679-A-006
-1.4
VS = 5
VS = +5
VS = +3
0.6
VS = +5V
-1.6
0.4
VS = +3V
-1.8
PNP ACTIVE
0.2
-2.0 -40
-25
-10
5
20 35 50 65 TEMPERATURE (C)
80
95
110
0 125
-25
-10
5
20 35 50 65 TEMPERATURE (C)
80
95
110
125
03679-0-073
Figure 38. Input Bias Current vs. Temperature
Figure 41. Input Offset Voltage vs. Temperature
1.8 1.7 1.6 VS = +5V
120 COUNT = 1088 MEAN = 0.44mV STDEV = 1.05mV 100
SUPPLY CURRENT (mA)
1.5 1.4 1.3
VS = 5V
80
FREQUENCY
80 100 120
03679-0-067
VS = +3V 1.2 1.1 1.0
60
40
20
0.9 0.8 -40 -20 0 20 40 60 TEMPERATURE (C)
0
-5
-4
-3
-2 -1 0 1 2 3 INPUT OFFSET VOLTAGE (mV)
4
5
03679-0-064
Figure 39 Quiescent Supply Current vs. Temperature
Figure 42. Input Offset Voltage Distribution
Rev. A | Page 12 of 20
AD8029/AD8030/AD8040
1M DISABLE = LOW 100k
OUTPUT IMPEDANCE () OUTPUT IMPEDANCE ()
1000 G = +1
100
10k
1k
10
100
1
10
1 100k
1M
10M FREQUENCY (Hz)
100M
1G
03679-0-061
0.1 1k
10k
100k 1M 10M FREQUENCY (Hz)
100M
1G
03679-0-060
Figure 43. AD8029 Output Impedance vs. Frequency, Disabled
Figure 45. Output Impedance vs. Frequency, Enabled
0.5 0.4 LOAD RESISTANCE TIED TO MIDSUPPLY
2.0 VS = 2.5V 1.5
OUTPUT SATURATION VOLTAGE (V)
INPUT ERROR VOLTAGE (mV)
0.3 0.2 0.1 0 -0.1 VOH - VS -0.2 -0.3 -0.4 -0.5 100 1000 LOAD RESISTANCE () 10000
03679-0-041
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 RL = 1k RL = 10k
VOL - VS VS = +5V VS = 5V
VS = +3V
-2.0
-1.5
-1.0 -0.5 -0 0.5 1.0 OUTPUT VOLTAGE (V)
1.5
2.0
2.5
03679-0-072
Figure 44. Output Saturation Voltage vs. Load Resistance
Figure 46. Input Error Voltage vs. Output Voltage
170 VS = 5V
OUTPUT SATURATION VOLTAGE (mV)
150
130
110 VS = +5V
90
70
50
VS = +3V
30 -40
RL = 1k TIED TO MIDSUPPLY SOLID LINE: VS+ - VOH DASHED LINE: VOL - VS- 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125
-25
-10
03679-0-066
Figure 42. Output Saturation Voltage vs. Temperature
Rev. A | Page 13 of 20
AD8029/AD8030/AD8040
1.5 DISABLE (-0.5V TO -2V)
0 1 VS = +3V, +5V, +10V
1.0
0.5 RL = 100 0 RL = 1k RL = 10k -0.5 OUTPUT DISABLED
DISABLE PIN CURRENT (A)
OUTPUT AMPLITUDE (V)
-1 -2 -3 -4 -5 -6 -7 0 0.8 1 1.2 2 DISABLE PIN VOLTAGE (V) 3
03679-A-022
-1.0 VS = 2.5V G = -1 (RF = 1k) 0 50 100 150 200 TIME (ns) 250 300 350
-1.5
03679-A-020
Figure 47. AD8029 DISABLE Turn-Off Timing
Figure 49. AD8029 DISABLE Pin Current vs. DISABLE Pin Voltage
1.5 DISABLE (-2V TO -0.5V) 1.0
OUTPUT AMPLITUDE (V)
OUTPUT ENABLED
0.5
0 RL = 100 RL = 1k RL = 10k
-0.5
-1.0 VS = 2.5V G = -1 (RF = 1k) 0 50 100 150 200 TIME (ns) 250 300 350
-1.5
03679-A-021
Figure 48. AD8029 DISABLE Turn-On Timing
Rev. A | Page 14 of 20
AD8029/AD8030/AD8040 THEORY OF OPERATION
+VS RTH DISABLE TO DISABLE CIRCUITRY +VS -1.2V Q9 ITH -VS Q10 Q1 IN- Q5 Q6 Q2 VOUT CMB Q7 IN+ Q8 Q3 Q4 MBOT R5 R6 R7 R8 Q11 MTOP CMT R1 R2 R3 R4 OUTPUT BUFFER SPD ITAIL
AD8029 ONLY
OUT COM
IN -VS
03679-0-051
Figure 50. Simplified Schematic
The AD8029 (single), AD8030 (dual), and AD8040 (quad) are rail-to-rail input and output amplifiers fabricated using Analog Devices' XFCB process. The XFCB process enables the AD8029/ AD8030/AD8040 to operate on 2.7 V to 12 V supplies with a 120 MHz bandwidth and a 60 V/s slew rate. A simplified schematic of the AD8029/AD8030/AD8040 is shown in Figure 50.
OUTPUT STAGE
The currents derived from the PNP and NPN input differential pairs are injected into the current mirrors MBOT and MTOP, thus establishing a common-mode signal voltage at the input of the output buffer. The output buffer performs three functions: 1. 2. 3. It buffers and applies the desired signal voltage to the output devices, Q10 and Q11. It senses the common-mode current level in the output devices. It regulates the output common-mode current by establishing a common-mode feedback loop.
INPUT STAGE
For input common-mode voltages less than a set threshold (1.2 V below VCC), the resistor degenerated PNP differential pair (comprising Q1 toQ4) carries the entire ITAIL current, allowing the input voltage to go 200 mV below -VS. Conversely, input common-mode voltages exceeding the same threshold cause ITAIL to be routed away from the PNP differential pair and into the NPN differential pair through transistor Q9. Under this condition, the input common-mode voltage is allowed to rise 200 mV above +VS while still maintaining linear amplifier behavior. The transition between these two modes of operation leads to a sudden, temporary shift in input stage transconductance, gm, and dc parameters (such as the input offset voltage VOS), which in turn adversely affect the distortion performance. The SPD block shortens the duration of this transition, thus improving the distortion performance. As shown in Figure 50, the input differential pair is protected by a pair of two series diodes, connected in anti-parallel, which clamp the differential input voltage to approximately 1.5 V.
The output devices Q10 and Q11 work in a common-emitter configuration, and are Miller-compensated by internal capacitors, CMT and CMB. The output voltage compliance is set by the output devices' collector resistance RC (about 25 ), and by the required load current IL. For instance, a light equivalent load (5 k) allows the output voltage to swing to within 40 mV of either rail, while heavier loads cause this figure to deteriorate as RC x IL.
Rev. A | Page 15 of 20
AD8029/AD8030/AD8040 APPLICATIONS
WIDEBAND OPERATION
RF +VS C2 10F C1 0.1F RG -
AD8029
VIN R1 + C4 0.1F C3 10F DISABLE
VOUT
For example, if using the values shown in Table 5 for a gain of 2, with resistor values of 2.5 k, the effective load at the output is 1.67 k. For inverting configurations, only the feedback resistor RF is in parallel with the output load. If the load is greater than that specified in the data sheet, the amplifier can introduce nonlinearities in its open-loop response, which increases distortion. Figure 53 and Figure 54 illustrate effective output loading and distortion performance. Increasing the resistance of the feedback network can reduce the current consumption, but has other implications.
-40 VS = 5V VOUT = 2.0V p-p 0.1V -50 SECOND HARMONIC - SOLID LINES THIRD HARMONIC - DOTTED LINES
HARMONIC DISTORTION (dBc)
R1 = RF||RG
-VS
03679-0-052
Figure 51. Wideband Non-inverting Gain Configuration
RF +VS C2 10F C1 0.1F VIN RG -
-60 -70 RL = 1k -80 -90 -100 RL = 2.5k -110 -120 0.01
03679-A-008 03679-A-009
RL = 5k
AD8029
+ R1 = RF||RG R1 C4 0.1F C3 10F
VOUT DISABLE
0.1 1.0 FREQUENCY (MHz)
10
Figure 53. Gain of 1 Distortion
-40
03679-0-053
-VS
Figure 52. Wideband Inverting Gain Configuration
HARMONIC DISTORTION (dBc)
VS = 5V VOUT = 2.0V p-p 0.1V -50 SECOND HARMONIC - SOLID LINES THIRD HARMONIC - DOTTED LINES -60 -70 -80 -90 -100 RF = RL = 2.5k -110 -120 0.01 RF = RL = 5k RF = RL = 1k
OUTPUT LOADING SENSITIVITY
To achieve maximum performance and low power dissipation, the designer needs to consider the loading at the output of AD8029/AD8030/AD8040. Table 5 shows the effects of output loading and performance. When operating at unity gain, the effective load at the amplifier output is the resistance (RL) being driven by the amplifier. For gains other than 1, in noninverting configurations, the feedback network represents an additional current load at the amplifier output. The feedback network (RF + RG) is in parallel with RL, which lowers the effective resistance at the output of the amplifier. The lower effective resistance causes the amplifier to supply more current at the output. Lower values of feedback resistance increase the current draw, thus increasing the amplifier's power dissipation.
0.1 1.0 FREQUENCY (MHz)
10
Figure 54. Gain of 2 Distortion
Rev. A | Page 16 of 20
AD8029/AD8030/AD8040
Table 5. Effect of Load on Performance
Noninverting Gain 1 1 1 2 2 2 -1 -1 -1 RF (k) 0 0 0 1 2.5 5 1 2.5 5 RG (k) N/A N/A N/A 1 2.5 5 1 2.5 5 RLOAD (k) 1 2 5 1 2.5 5 1 2.5 5 -3 dB SS BW (MHz) 120 130 139 36 44.5 43 40 40 34 Peaking (dB) 0.02 0.6 1 0 0.2 2 0.01 0.05 1 HD2 at 1 MHz, 2 V p-p (dB) -80 -84 -87.5 -72 -79 -84 -68 -74 -78 HD3 at 1 MHz, 2 V p-p (dB) -72 -83 -92.5 -60 -72.5 -86 -57 -68 -80 Output Noise (nV/Hz) 16.5 16.5 16.5 33.5 34.4 36 33.6 34 36
The feedback resistance (RF || RG) combines with the input capacitance to form a pole in the amplifier's loop response. This can cause peaking and ringing in the amplifier's response if the RC time constant is too low. Figure 55 illustrates this effect. Peaking can be reduced by adding a small capacitor (1 pF-4 pF) across the feedback resistor. The best way to find the optimal value of capacitor is to empirically try it in your circuit. Another factor of higher resistance values is the impact it has on noise performance. Higher resistor values generate more noise. Each application is unique and therefore a balance must be reached between distortion, peaking, and noise performance. Table 5 outlines the trade-offs that different loads have on distortion, peaking, and noise performance. In gains of 1, 2, and 10, equivalent loads of 1 k, 2 k, and 5 k are shown. With increasing load resistance, the distortion and -3 dB bandwidth improve, while the noise and peaking degrade slightly.
2 VS = 5V VOUT = 0.1V p-p
DISABLE PIN
The AD8029 disable pin allows the amplifier to be shut down for power conservation or multiplexing applications. When in the disable mode, the amplifier draws only 150 A of quiescent current. The disable pin control voltage is referenced to the negative supply. The amplifier enters power-down mode any time the disable pin is tied to the most negative supply or within 0.8 V of the negative supply. If left open, the amplifier will operate normally. For switching levels, refer to Table 6. Table 6. Disable Pin Control Voltage
Disable Pin Voltage Low (Disabled) High (Enabled) Supply Voltage +3 V 0 V to <0.8 V 1.2 V to 3 V +5 V 0 V to <0.8 V 1.2 V to 5 V 5 V -5 V to <-4 .2 V -3.8 V to +5 V
NORMALIZED CLOSED-LOOP GAIN (dB)
1 0 -1 -2 -3 -4
RF = RL = 5k RL = 1k RL = 2.5k
RF = RL = 2.5k RF = RL = 1k
RL = 5k
G = +1 -5 -6 -7 -8 1 10 100 FREQUENCY (MHz) 1000
03679-A-007
G = +2
Figure 55. Frequency Response for Various Feedback/Load Resistances
Rev. A | Page 17 of 20
AD8029/AD8030/AD8040
CIRCUIT CONSIDERATIONS
PCB Layout
High speed op amps require careful attention to PCB layout to achieve optimum performance. Particular care must be exercised to minimize lead lengths of the bypass capacitors. Excess lead inductance can influence the frequency response and even cause high frequency oscillations. Using a multilayer board with an internal ground plane can help reduce ground noise and enable a more compact layout. To achieve the shortest possible trace length at the inverting input, the feedback resistor, RF, should be located the shortest distance from the output pin to the input pin. The return node of the resistor RG should be situated as close as possible to the return node of the negative supply bypass capacitor. On multilayer boards, all layers beneath the op amp should be cleared of metal to avoid creating parasitic capacitive elements. This is especially true at the summing junction, i.e., the inverting input, -IN. Extra capacitance at the summing junction can cause increased peaking in the frequency response and lower phase margin.
Power Supply Bypassing
Power supply pins are actually inputs to the op amp. Care must be taken to provide the op amp with a clean, low noise dc voltage source. Power supply bypassing is employed to provide a low impedance path to ground for noise and undesired signals at all frequencies. This cannot be achieved with a single capacitor type; but with a variety of capacitors in parallel the bandwidth of power supply bypassing can be greatly extended. The bypass capacitors have two functions: 1. 2. Provide a low impedance path for noise and undesired signals from the supply pins to ground. Provide local stored charge for fast switching conditions and minimize the voltage drop at the supply pins during transients. This is typically achieved with large electrolytic capacitors.
Grounding
To minimize parasitic inductances and ground loops in high speed, densely populated boards, a ground plane layer is critical. Understanding where the current flows in a circuit is critical in the implementation of high speed circuit design. The length of the current path is directly proportional to the magnitude of the parasitic inductances and thus the high frequency impedance of the path. Fast current changes in an inductive ground return will create unwanted noise and ringing. The length of the high frequency bypass capacitor pads and traces is critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Because load currents flow from supplies as well as from ground, the load should be placed at the same physical location as the bypass capacitor ground. For large values of capacitors, which are intended to be effective at lower frequencies, the current return path length is less critical.
Good quality ceramic chip capacitors should be used and always kept as close as possible to the amplifier package. A parallel combination of a 0.1 F ceramic and a 10 F electrolytic covers a wide range of rejection for unwanted noise. The 10 F capacitor is less critical for high frequency bypassing and, in most cases, one per supply line is sufficient. The values of capacitors are circuit-dependant and should be determined by the system's requirements.
DESIGN TOOLS AND TECHNICAL SUPPORT
Analog Devices is committed to the design process by providing technical support and online design tools. ADI offers technical support via free evaluation boards, sample ICs, Spice models, interactive evaluation tools, application notes, phone and email support--all available at www.analog.com.
Rev. A | Page 18 of 20
AD8029/AD8030/AD8040 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5 4
14 1
8.75 (0.3445) 8.55 (0.3366)
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440) 5.80 (0.2284)
4.00 (0.1575) 3.80 (0.1496)
8 7
6.20 (0.2441) 5.80 (0.2283)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.25 (0.0098) 0.10 (0.0039)
1.27 (0.0500) BSC
1.75 (0.0689) 1.35 (0.0531)
0.50 (0.0197) x 45 0.25 (0.0098)
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COPLANARITY 0.10
0.51 (0.0201) 0.31 (0.0122)
SEATING PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 56. 8-Lead Standard Small Outline Package, Narrow Body [SOIC] (R-8) Dimensions shown in millimeters and (inches)
Figure 59. 14-Lead Standard Small Outline Package [SOIC] (R-14) Dimensions shown in millimeters and (inches)
2.00 BSC
5.10 5.00 4.90
4
6
5 2
1.25 BSC
1 3
2.10 BSC
4.50 4.40 4.30
14
8
PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 1.10 MAX 0.22 0.08 0.30 0.15 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203AB SEATING PLANE 8 4 0
6.40 BSC
1 7
PIN 1
0.10 MAX
0.46 0.36 0.26
1.05 1.00 0.80
0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 8 0 0.75 0.60 0.45
SEATING COPLANARITY PLANE 0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 57. 6-Lead Plastic Surface-Mount Package [SC70] (KS-6) Dimensions shown in millimeters
Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
2.90 BSC
8
7
6
5
1.60 BSC
1 2 3 4
2.80 BSC
PIN 1 0.65 BSC 1.30 1.15 0.90 1.95 BSC
1.45 MAX
0.22 0.08 8 4 0
0.15 MAX
0.38 0.22
SEATING PLANE
0.60 0.45 0.30
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 58. 8-Lead Small Outline Transistor Package [SOT23] (RJ-8) Dimensions shown in millimeters
Rev. A | Page 19 of 20
AD8029/AD8030/AD8040 ORDERING GUIDE
Model AD8029AR AD8029AR-REEL AD8029AR-REEL7 AD8029AKS-R2 AD8029AKS-REEL AD8029AKS-REEL7 AD8030AR AD8030AR-REEL AD8030AR-REEL7 AD8030ARJ-R2 AD8030ARJ-REEL AD8030ARJ-REEL7 AD8040AR AD8040AR-REEL AD8040AR-REEL7 AD8040ARU AD8040ARU-REEL AD8040ARU-REEL7 Minimum Ordering Quantity 1 2,500 1,000 250 10,000 3,000 1 2,500 1,000 250 10,000 3,000 1 2500 1000 1 2500 1000 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 6-Lead SC70 6-Lead SC70 6-Lead SC70 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOT23-8 8-Lead SOT23-8 8-Lead SOT23-8 14-Lead SOIC 14-Lead SOIC 14-Lead SOIC 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Package Option R-8 R-8 R-8 KS-6 KS-6 KS-6 R-8 R-8 R-8 RJ-8 RJ-8 RJ-8 R-14 R-14 R-14 RU-14 RU-14 RU-14 Branding
H6B H6B H6B
H7B H7B H7B
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03679-0-11/03(A)
Rev. A | Page 20 of 20

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